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d a t a sh eet product speci?cation file under integrated circuits, ic22 1999 may 31 integrated circuits SAA7126H; saa7127h digital video encoder
1999 may 31 2 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h features monolithic cmos 3.3 v device, 5 v i 2 c-bus optionally digital pal/ntsc encoder system pixel frequency 13.5 mhz 54 mhz double-speed multiplexed d1 interface capable of splitting data into two separate channels (encoded and baseband) four digital-to-analog converters (dacs) for cvbs (csync, vbs), red (cr, c), green (y, vbs) and blue (cb, cvbs) two times oversampled (signals in parenthesis are optionally). red (cr), green (y) and blue (cb) signal outputs with 9-bit resolution, whereas all other signal outputs have 10-bit resolution; csync is an advanced composite sync on the cvbs output for rgb display centring. real-time control of subcarrier cross-colour reduction filter closed captioning encoding and world standard teletext (wst) and north-american broadcast text system (nabts) teletext encoding including sequencer and filter copy generation management system (cgms) encoding (cgms described by standard cpr-1204 of eiaj); 20 bits in lines 20/283 (ntsc) can be loaded via the i 2 c-bus fast i 2 c-bus control port (400 khz) line 23 wide screen signalling (wss) encoding video programming system (vps) data encoding in line 16 (ccir line count) encoder can be master or slave programmable horizontal and vertical input synchronization phase programmable horizontal sync output phase internal colour bar generator (cbg) macrovision pay-per-view copy protection system rev. 7.01 and rev. 6.1 as option; handsfree macrovision pulse support through on-chip timer for pulse amplitude modulation; this applies to SAA7126H only. the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only. reverse engineering or disassembly is prohibited. please contact your nearest philips semiconductors sales office for more information. controlled rise/fall times of output syncs and blanking on-chip crystal oscillator (3rd-harmonic or fundamental crystal) down mode (low output voltage) or power-save mode of dacs qfp44 package. general description the SAA7126H; saa7127h encodes digital cb-y-cr video data to an ntsc or pal cvbs or s-video signal. simultaneously, rgb or bypassed but interpolated cb-y-cr signals are available via three additional digital-to-analog converters (dacs). the circuit at a 54 mhz multiplexed digital d1 input port accepts two ccir compatible cb-y-cr data streams with 720 active pixels per line in 4 :2:2 multiplexed formats, for example mpeg decoded data with overlay and mpeg decoded data without overlay, whereas one data stream is latched at the rising, the other one at the falling clock edge. it includes a sync/clock generator and on-chip dacs. ordering information type number package name description version SAA7126H qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 saa7127h
1999 may 31 3 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h quick reference data block diagram symbol parameter min. typ. max. unit v dda analog supply voltage 3.15 3.3 3.45 v v ddd digital supply voltage 3.0 3.3 3.6 v i dda analog supply current - 77 100 ma i ddd digital supply current - 37 46 ma v i input signal voltage levels ttl compatible v o(p-p) analog output signal voltages y, c and cvbs without load (peak-to-peak value) 1.30 1.45 1.55 v r l load resistance 75 - 300 w le lf(i) low frequency integral linearity error -- 3 lsb le lf(d) low frequency differential linearity error -- 1 lsb t amb ambient temperature 0 - 70 c fig.1 block diagram. handbook, full pagewidth i 2 c-bus interface data manager encoder sync/clock output interface d a 40 42 41 7 84337 34 35 4 mp7 to mp0 ttx v dd(i2c) 19 30 23 26 reset sda scl rcv1 rcv2 ttxrq xclk xtal xtali llc1 cvbs red green 29 blue i 2 c-bus control i 2 c-bus control i 2 c-bus control i 2 c-bus control i 2 c-bus control 5 v ssd1 18 v ssd2 38 v ssd3 6 v ddd1 17 v ddd2 39 v ddd3 22 v ssa1 32 v ssa2 33 v ssa3 25 v dda1 28 v dda2 31 v dda3 36 v dda4 rtci 23 sp ap clock and timing y y c rgb processor i 2 c-bus control y cbcr cbcr 44 20 sa 21 res 1 n.c. 24, 27 9 to 16 mp1 mp2 mhb498 SAA7126H saa7127h
1999 may 31 4 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h pinning symbol type pin description res - 1 reserved pin; do not connect sp i 2 test pin; connected to digital ground for normal operation ap i 3 test pin; connected to digital ground for normal operation llc1 i 4 line-locked clock input; this is the 27 mhz master clock v ssd1 - 5 digital ground 1 v ddd1 - 6 digital supply voltage 1 rcv1 i/o 7 raster control 1 for video port; this pin receives/provides a vs/fs/fseq signal rcv2 i/o 8 raster control 2 for video port; this pin provides an hs pulse of programmable length or receives an hs pulse mp7 i 9 double-speed 54 mhz mpeg port; it is an input for ccir 656 style multiplexed cb-y-cr data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is then sent to the encoding part of the device; data sampled on the falling edge is sent to the rgb part of the device (or vice versa, depending on programming) mp6 i 10 mp5 i 11 mp4 i 12 mp3 i 13 mp2 i 14 mp1 i 15 mp0 i 16 v ddd2 - 17 digital supply voltage 2 v ssd2 - 18 digital ground 2 rtci i 19 real-time control input (i 2 c-bus register sres = 0): if the llc1 clock is provided by an saa7111 or saa7151b, rtci should be connected to the rtco pin of the respective decoder to improve the signal quality. sync reset input (i 2 c-bus register sres = 1): a high impulse resets synchronization of the encoder (?rst ?eld, ?rst line). v dd(i2c) - 20 sense input for i 2 c-bus voltage; connect to i 2 c-bus supply sa i 21 select i 2 c-bus address; low selects slave address 88h, high selects slave address 8ch v ssa1 - 22 analog ground 1 for red (cr) (c) and green (y) (vbs) outputs red o 23 analog output of red (cr) or (c) signal n.c. - 24 not connected v dda1 - 25 analog supply voltage 1 for red (cr) (c) output green o 26 analog output of green (y) or (vbs) signal n.c. - 27 not connected v dda2 - 28 analog supply voltage 2 for green (y) (vbs) output blue o 29 analog output of blue (cb) or (cvbs) signal cvbs o 30 analog output of cvbs (csync) or (vbs) signal v dda3 - 31 analog supply voltage 3 for blue (cb) (cvbs) and cvbs (csync) (vbs) outputs v ssa2 - 32 analog ground 2 for blue (cb) (cvbs) and cvbs (csync) (vbs) outputs v ssa3 - 33 analog ground 3 for the dac reference ladder and the oscillator xtal o 34 crystal oscillator output xtali i 35 crystal oscillator input; if the oscillator is not used, this pin should be connected to ground v dda4 - 36 analog supply voltage 4 for the dac reference ladder and the oscillator
1999 may 31 5 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h xclk o 37 clock output of the crystal oscillator v ssd3 - 38 digital ground 3 v ddd3 - 39 digital supply voltage 3 reset i 40 reset input, active low. after reset is applied, all digital i/os are in input mode; pal black burst on cvbs, vbs and c; rgb outputs set to lowest voltage. the i 2 c-bus receiver waits for the start condition. scl i 41 i 2 c-bus serial clock input sda i/o 42 i 2 c-bus serial data input/output ttxrq o 43 teletext request output, indicating when text bits are requested ttx i 44 teletext bit stream input symbol type pin description fig.2 pin configuration. handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 SAA7126H saa7127h mhb499 v ssa3 v ssa2 v dda3 cvbs v dda2 n.c. green v dda1 n.c. red res sp ap llc1 v ssd1 v ddd1 rcv2 mp7 mp5 blue ttxrq sda scl reset v ddd3 v ssd3 v dda4 xtali xtal ttx xclk mp3 mp2 mp1 mp0 v ddd2 v ssd2 v dd(i2c) sa v ssa1 mp4 rtci rcv1 mp6
1999 may 31 6 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h functional description the digital video encoder encodes digital luminance and colour difference signals into analog cvbs, s-video and simultaneously rgb or cr-y-cb signals. ntsc-m, pal b/g and sub-standards are supported. both interlaced and non-interlaced operation is possible for all standards. the basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals. luminance and chrominance signals are filtered in accordance with the standard requirements of rs-170-a and itu-r bt.470-3 . for ease of analog post filtering the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. the total filter transfer characteristics are illustrated in figs 3 to 8. the dacs for y, c and cvbs are realized with full 10-bit resolution; 9-bit resolution for rgb output. the cr-y-cb to rgb dematrix can be bypassed optionally in order to provide the upsampled cr-y-cb input signals. the 8-bit multiplexed cb-y-cr formats are ccir 656 (d1 format) compatible, but the sav and eav codes can be decoded optionally; when the device is operated in slave mode. two independent data streams can be processed, one latched by the rising edge of llc1, the other latched by the falling edge of llc1. the purpose of that is e.g. to forward one of the data streams containing both video and on screen display (osd) information to the rgb outputs, and the other stream containing video only to the encoded outputs cvbs and s-video. for optimum display of rgb signals through a euro-connector tv set, an early composite sync pulse (up to 31llc1 clock periods) can be provided optionally on the cvbs output. it is also possible to connect a philips digital video decoder (saa7111, saa7711a, saa7112 or saa7151b) to the SAA7126H; saa7127h. information concerning the actual subcarrier, pal-id and (with saa7111 and newer types) definite subcarrier phase can be inserted via the rtci pin, connected to the rtco pin of a decoder. the SAA7126H; saa7127h synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. wide screen signalling data can be loaded via the i 2 c-bus and is inserted into line 23 for standards using a 50 hz field rate. vps data for program dependent automatic start and stop of such featured vcrs is loadable via the i 2 c-bus. the ic also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with macrovision. it is also possible to load data for copy generation management system into line 20 of every field (525/60 line counting). a number of possibilities are provided for setting different video parameters such as: black and blanking level control colour subcarrier frequency variable burst amplitude etc. during reset ( reset = low) and after reset is released, all digital i/o stages are set to the input mode and the encoder is set to pal mode and outputs a black burst signal on cvbs and s-video outputs, while rgb outputs are set to their lowest output voltages. a reset forces the i 2 c-bus interface to abort any running bus transfer. data manager in the data manager, alternatively to the external video data, a pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without need for an external data source. encoder v ideo path the encoder generates out of y, u and v baseband signals luminance and colour subcarrier output signals, suitable for use as cvbs or separate y and c signals. luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes, a blanking level can be set. other manipulations used for the macrovision anti-taping process such as additional insertion of agc super-white pulses (programmable in height) are supported by SAA7126H only. in order to enable easy analog post filtering, luminance is interpolated from 13.5 mhz data rate to 27 mhz data rate, providing luminance in 10-bit resolution. the transfer characteristic of the luminance interpolation filter are illustrated in figs 5 and 6. appropriate transients at start/end of active video and for synchronization pulses are ensured.
1999 may 31 7 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h chrominance is modified in gain (programmable separately for u and v), standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 mhz data rate to a 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for y and c output. the transfer characteristics of the chrominance interpolation filter are illustrated in figs 3 and 4. the amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on the subcarrier. the numeric ratio between the y and c outputs is in accordance with set standards. t eletext insertion and encoding pin ttx receives a wst or nabts teletext bitstream sampled at the llc clock. two protocols are provided: at each rising edge of output signal (ttxrq) a single teletext bit has to be provided after a programmable delay at input pin ttx. or: the signal ttxrq performs only a single low-to-high transition and remains at high level for 360, 296 or 288 teletext bits, depending on the chosen standard. phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. ttxrq provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which are selectable independently for both fields. the internal insertion window for text is set to 360 (pal-wst), 296 (ntsc-wst) or 288 (nabts) teletext bits including clock run-in bits. the protocol and timing are illustrated in fig.14. v ideo p rogramming s ystem (vps) encoding five bytes of vps information can be loaded via the i 2 c-bus and will be encoded in the appropriate format into line 16. c losed caption encoder using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. the actual line number where data is to be encoded in, can be modified in a certain range. the data clock frequency is in accordance with the definition for ntsc-m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz field frequencies at 32 times the horizontal line frequency. a nti - taping (SAA7126H only ) for more information contact your nearest philips semiconductors sales office. rgb processor this block contains a dematrix in order to produce red, green and blue signals to be fed to a scart plug. before y, cb and cr signals are de-matrixed, individual gain adjustment for y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. the transfer curves of luminance and colour difference components of rgb are illustrated in figs 7 and 8. output interface/dacs in the output interface, encoded y and c signals are converted from digital-to-analog in a 10-bit resolution. y and c signals are also combined to a 10-bit cvbs signal. the cvbs output occurs with the same processing delay (equal to 51 llc clock periods, measured from mp input to the analog outputs) as the y, c and rgb outputs. absolute amplitude at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of conversion ranges. red, green and blue signals are also converted from digital-to-analog, each providing a 9-bit resolution. outputs of the dacs can be set together via software control to minimum output voltage (approximately 0.2 v dc) for either purpose. alternatively, the buffers can be switched into 3-state output condition; this allows for wired anding with other 3-state outputs and can also be used as a power-save mode.
1999 may 31 8 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h synchronization the synchronization of the SAA7126H; saa7127h is able to operate in two modes; slave mode and master mode. in master mode (see fig.10), the circuit generates all necessary timings in the video signal itself, and it can provide timing signals at the rcv1 and rcv2 ports. in slave mode, it accepts timing information either from the rcv pins or from the embedded timing data of the ccir 656 data stream. for the SAA7126H; saa7127h, the only difference between master and slave mode is that it ignores the timing information at its inputs in master mode. thus, if in slave mode, any timing information is missing, the ic will continue running free without a visible effect. but there must not be any additional pulses (with wrong phase) because the circuit will not ignore them. in slave mode (see fig.9), an interface circuit decides, which signal is expected at the rcv1 port and which information is taken from its active slope. the polarity can be chosen, if prcv1 is logic 0 the rising slope will be active. the signal can be: a vertical sync (vs) pulse; the active slope sets the vertical phase an odd/even signal; the active slope sets the vertical phase, the internal field flag to odd and optionally sets the horizontal phase a field sequence (fseq) signal; it marks the first field of the 4 (ntsc) or 8 (pal) field sequence. in addition to the odd/even signal, it also sets the pal phase and optionally defines the subcarrier phase. on the rcv2 port, the ic can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. the horizontal phase can be set via a separate input rcv2. in the event of vs pulses at rcv1, this is mandatory. it is also possible to set the signal path to blank via this input. from the ccir 656 data stream, the SAA7126H; saa7127h decodes only the start of the first line in the odd field. all other information is ignored and may miss. if this kind of slave mode is active, the rcv pins may be switched to output mode. in slave mode, the horizontal trigger phase can be programmed to any point in the line, the vertical phase from line 0 to line 15 counted from the first serration pulse in half line steps. whenever a synchronization information cannot be derived directly from the inputs, the SAA7126H; saa7127h will calculate it from the internal horizontal, vertical and pal phase. this gives good flexibility with respect to external synchronization but the circuit does not suppress illegal settings. in such an event, e.g the odd/even information may vanish as it does in the non-interlaced modes. in master mode, the line lengths are fixed to 1728 clocks at 50 hz and 1716 clocks at 60 hz. to allow non-interlaced frames, the field lengths can be varied by 0.5 lines. in the event of non-interlace, the SAA7126H; saa7127h does not provide odd/even information and the output signal does not contain the pal bruch sequence. at the rcv1 pin the ic can provide: a vertical sync (vs) signal with 2.5 (50 hz) or 3 (60 hz) lines duration an odd/even signal which is low in odd fields a field sequence (fseq) signal which is high in the first field of the 4 or 8 field sequence. at the rcv2 pin, there is a horizontal pulse of programmable phase and duration available. this pulse can be suppressed in the programmable inactive part of a field giving a composite blank signal. the directions and polarities of the rcv ports can be chosen independently. timing references can be found in tables 29 and 37. clock the input at llc1 can either be an external clock source or the buffered on-chip clock xclk. the internal crystal oscillator can be run with either a 3rd-harmonic or a fundamental crystal. i 2 c-bus interface the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write and readable, except one read only status byte. the i 2 c-bus slave address is defined as 88h with pin 21 (sa) tied low and as 8ch with pin 21 (sa) tied high.
1999 may 31 9 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h input levels and formats the SAA7126H; saa7127h expects digital y, cb, cr data with levels (digital codes) in accordance with ccir 601 . for c and cvbs outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 ire set-up or without set-up. the rgb, respectively cr-y-cb path features a gain setting individually for luminance (gy) and colour difference signals (gcd). reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. table 1 ccir 601 signal component levels notes 1. transformation: a) r = y + 1.3707 (cr - 128) b) g = y - 0.3365 (cb - 128) - 0.6982 (cr - 128) c) b = y + 1.7324 (cb - 128). 2. representation of r, g and b (or cr, y and cb) at the output is 9 bits at 27 mhz. table 2 8-bit multiplexed format (similar to ccir 601 ) colour signals (1) ycbcrr (2) g (2) b (2) white 235 128 128 235 235 235 yellow 210 16 146 235 235 16 cyan 170 166 16 16 235 235 green 145 54 34 16 235 16 magenta 106 202 222 235 16 235 red 81 90 240 235 16 16 blue 41 240 110 16 16 235 black 16 128 128 16 16 16 time bits 01234567 sample cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 y 3 luminance pixel number 0123 colour pixel number 0 2
1999 may 31 10 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... bit allocation map table 3 slave receiver (slave address 88h) register function sub addr (hex) data byte (1) d7 d6 d5 d4 d3 d2 d1 d0 status byte (read only) 00h ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e null 01h to 25h 00000000 wide screen signal 26h wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 wide screen signal 27h wsson 0 wss13 wss12 wss11 wss10 wss9 wss8 real-time control, burst start 28h deccol decfis bs5 bs4 bs3 bs2 bs1 bs0 sync reset enable, burst end 29h sres 0 be5 be4 be3 be2 be1 be0 copy generation 0 2ah cg07 cg06 cg05 cg04 cg03 cg02 cg01 cg00 copy generation 1 2bh cg15 cg14 cg13 cg12 cg11 cg10 cg09 cg08 cg enable, copy generation 2 2ch cgen 0 0 0 cg19 cg18 cg17 cg16 output port control 2dh vbsen1 vbsen0 cvbsen cen cvbstri rtri gtri btri null 2eh to 37h 00000000 gain luminance for rgb 38h 0 0 0 gy4 gy3 gy2 gy1 gy0 gain colour difference for rgb 39h 0 0 0 gcd4 gcd3 gcd2 gcd1 gcd0 input port control 1 3ah cbenb 0 0 symp demoff csync mp2c2 mp2c1 vps enable, input control 2 54h vpsen ccirs 0000 edge2 edge1 vps byte 5 55h vps57 vps56 vps55 vps54 vps53 vps52 vps51 vps50 vps byte 11 56h vps117 vps116 vps115 vps114 vps113 vps112 vps111 vps110 vps byte 12 57h vps127 vps126 vps125 vps124 vps123 vps122 vps121 vps120 vps byte 13 58h vps137 vps136 vps135 vps134 vps133 vps132 vps131 vps130 vps byte 14 59h vps147 vps146 vps145 vps144 vps143 vps142 vps141 vps140 chrominance phase 5ah chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0 gain u 5bh gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5ch gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, real-time control, black level 5dh gainu8 decoe blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, real-time control, blanking level 5eh gainv8 decph blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 ccr, blanking level vbi 5fh ccrs1 ccrs0 blnvb5 blnvb4 blnvb3 blnvb2 blnvb1 blnvb0 null 60h 00000000 standard control 61h downb downa inpi ygs 0 scbw pal fise
1999 may 31 11 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... note 1. all bits labelled 0 are reserved. they must be programmed with logic 0. rtc enable, burst amplitude 62h rtce bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63h fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64h fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65h fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66h fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67h l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68h l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69h l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6ah l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 rcv port control 6bh srcv11 srcv10 trcv2 orcv1 prcv1 cblf orcv2 prcv2 trigger control 6ch htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 trigger control 6dh htrig10 htrig9 htrig8 vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 multi control 6eh sblbn blckon phres1 phres0 ldel1 ldel0 flc1 flco closed caption, teletext enable 6fh ccen1 ccen0 ttxen sccln4 sccln3 sccln2 sccln1 sccln0 rcv2 output start 70h rcv2s7 rcv2s6 rcv2s5 rcv2s4 rcv2s3 rcv2s2 rcv2s1 rcv2s0 rcv2 output end 71h rcv2e7 rcv2e6 rcv2e5 rcv2e4 rcv2e3 rcv2e2 rcv2e1 rcv2e0 msbs rcv2 output 72h 0 rcv2e10 rcv2e9 rcv2e8 0 rcv2s10 rcv2s9 rcv2s8 ttx request h start 73h ttxhs7 ttxhs6 ttxhs5 ttxhs4 ttxhs3 ttxhs2 ttxhs1 ttxhs0 ttx request h delay, length 74h ttxhl3 ttxhl2 ttxhl1 ttxhl0 ttxhd3 ttxhd2 ttxhd1 ttxhd0 csync advance, vsync shift 75h csynca4 csynca3 csynca2 csynca1 csynca0 vs_s2 vs_s1 vs_s0 ttx odd request vertical start 76h ttxovs7 ttxovs6 ttxovs5 ttxovs4 ttxovs3 ttxovs2 ttxovs1 ttxovs0 ttx odd request vertical end 77h ttxove7 ttxove6 ttxove5 ttxove4 ttxove3 ttxove2 ttxove1 ttxove0 ttx even request vertical start 78h ttxevs7 ttxevs6 ttxevs5 ttxevs4 ttxevs3 ttxevs2 ttxevs1 ttxevs0 ttx even request vertical end 79h ttxeve7 ttxeve6 ttxeve5 ttxeve4 ttxeve3 ttxeve2 ttxeve1 ttxeve0 first active line 7ah fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7bh lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 ttx mode, msb vertical 7ch ttx60 lal8 ttxo fal8 ttxeve8 ttxove8 ttxevs8 ttxovs8 null 7dh 00000000 disable ttx line 7eh line12 line11 line10 line9 line8 line7 line6 line5 disable ttx line 7fh line20 line19 line18 line17 line16 line15 line14 line13 register function sub addr (hex) data byte (1) d7 d6 d5 d4 d3 d2 d1 d0
1999 may 31 12 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h i 2 c-bus format table 4 i 2 c-bus address; see table 5 table 5 explanation of table 4 notes 1. x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read. 2. if more than 1 byte of data is transmitted, then auto-increment of the subaddress is performed. slave receiver table 6 subaddresses 26h and 27h table 7 subaddress 28h s slave address ack subaddress ack data 0 ack -------- data n ack p part description s start condition slave address 1000100x or 1 0 0 0 1 1 0 x; note 1 ack acknowledge, generated by the slave subaddress; note 2 subaddress byte data data byte -------- continued data bytes and acks p stop condition data byte logic level description wss - wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved wsson 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled data byte logic level description remarks bs - starting point of burst in clock cycles pal: bs = 33 (21h); default after reset ntsc: bs = 25 (19h) deccol 0 disable colour detection bit of rtci input 1 enable colour detection bit of rtci input bit rtce must be set to logic 1 (see fig.13) decfis 0 ?eld sequence as fise in subaddress 61 1 ?eld sequence as fise bit in rtci input bit rtce must be set to logic 1 (see fig.13)
1999 may 31 13 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 8 subaddress 29h table 9 subaddresses 2ah to 2ch table 10 subaddress 2dh data byte logic level description remarks be - ending point of burst in clock cycles pal: be = 29 (1dh); default after reset ntsc: be = 29 (1dh) sres 0 pin 19 is real-time control input (rtci) 1 pin 19 is sync reset input (sres) a high impulse resets synchronization of the encoder (?rst ?eld, ?rst line) data byte logic level description cg - lsb of the respective bytes are encoded immediately after run-in, the msbs of the respective bytes have to carry the crcc bits, in accordance with the de?nition of copy generation management system encoding format. cgen 0 copy generation data output is disabled; default after reset 1 copy generation data output is enabled data byte logic level description btri 0 dac for blue output in 3-state mode (high-impedance) 1 dac for blue output in normal operation mode; default after reset gtri 0 dac for green output in 3-state mode (high-impedance) 1 dac for green output in normal operation mode; default after reset rtri 0 dac for red output in 3-state mode (high-impedance) 1 dac for red output in normal operation mode; default after reset cvbstri 0 dac for cvbs output in 3-state mode (high-impedance) 1 dac for cvbs output in normal operation mode; default after reset cen 0 red output signal is switched to r dac; default after reset 1 chrominance output signal is switched to r dac cvbsen 0 blue output signal is switched to b dac; default after reset 1 cvbs output signal is switched to b dac vbsen0 0 if csync = 0, cvbs output signal is switched to cvbs dac; default after reset 1 if csync = 0, luminance (vbs) output signal is switched to cvbs dac vbsen1 0 green output signal is switched to g dac; default after reset 1 luminance (vbs) output signal is switched to g dac
1999 may 31 14 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 11 subaddresses 38h and 39h table 12 subaddress 3ah table 13 subaddress 54h data byte description gy0 to gy4 gain luminance of rgb (cr, y and cb) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = - 6 (11010b), depending on external application. gcd0 to gcd4 gain colour difference of rgb (cr, y and cb) output, ranging from (1 - 16 32 )to(1+ 15 32 ). suggested nominal value = - 6 (11010b), depending on external application. data byte logic level description mp2c1 0 input data is twos complement from mp1 input port (encoder path) 1 input data is straight binary from mp1 input port; default after reset mp2c2 0 input data is twos complement from mp2 input port (rgb path) 1 input data is straight binary from mp2 input port; default after reset csync 0 if vbsen0 = 0, cvbs output signal is switched to cvbs dac. if vbsen0 = 1, luminance output signal is switched to cvbs dac; default after reset. 1 advanced composite sync is switched to cvbs dac demoff 0 y, cb and cr for rgb dematrix is active; default after reset 1 y, cb and cr for rgb dematrix is bypassed symp 0 horizontal and vertical trigger is taken from rcv2 and rcv1 respectively; default after reset 1 horizontal and vertical trigger is decoded out of ccir 656 compatible data at mp port cbenb 0 data from input ports is encoded; default after reset 1 colour bar with ?xed colours is encoded data byte logic level description edge1 0 mp1 data is sampled on the rising clock edge; default after reset 1 mp1 data is sampled on the falling clock edge edge2 0 mp2 data is sampled on the rising clock edge; default after reset 1 mp2 data is sampled on the falling clock edge ccirs 0 if symp = 1, horizontal and vertical trigger is decoded out of ccir 656 compatible data at mp2 port; default after reset. 1 if symp = 1, horizontal and vertical trigger is decoded out of ccir 656 compatible data at mp1 port. vpsen 0 video programming system data insertion is disabled; default after reset 1 video programming system data insertion in line 16 is enabled
1999 may 31 15 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 14 subaddresses 55h to 59h table 15 subaddress 5ah table 16 subaddresses 5bh and 5dh table 17 subaddresses 5ch and 5eh data byte description remarks vps5 ?fth byte of video programming system data lsbs of the respective bytes are encoded immediately after run-in and framing code in line 16; all other bytes are not relevant for vps vps11 eleventh byte of video programming system data vps12 twelfth byte of video programming system data vps13 thirteenth byte of video programming system data vps14 fourteenth byte of video programming system data data byte description value result chps phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 6bh pal-b/g and data from input ports 95h pal-b/g and data from look-up table a3h ntsc-m and data from input ports 46h ntsc-m and data from look-up table data byte description conditions remarks gainu variable gain for cb signal; input representation in accordance with ccir 601 white-to-black = 92.5 ire gainu = - 2.17 nominal to +2.16 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire gainu = - 2.05 nominal to +2.04 nominal gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal data byte description conditions remarks gainv variable gain for cr signal; input representation in accordance with ccir 601 white-to-black = 92.5 ire gainv = - 1.55 nominal to +1.55 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire gainv = - 1.46 nominal to +1.46 nominal gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal
1999 may 31 16 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 18 subaddress 5dh notes 1. output black level/ire = blckl 2/6.29 + 28.9. 2. output black level/ire = blckl 2/6.18 + 26.5. table 19 subaddress 5eh notes 1. output black level/ire = blnnl 2/6.29 + 25.4. 2. output black level/ire = blnnl 2/6.18 + 25.9; default after reset: 35h. table 20 subaddress 5fh data byte description conditions remarks blckl variable black level; input representation in accordance with ccir 601 white-to-sync = 140 ire; note 1 recommended value: blckl = 58 (3ah) blckl = 0; note 1 output black level = 29 ire blckl = 63 (3fh); note 1 output black level = 49 ire white-to-sync = 143 ire; note 2 recommended value: blckl = 51 (33h) blckl = 0; note 2 output black level = 27 ire blckl = 63 (3fh); note 2 output black level = 47 ire decoe real-time control logic 0 disable odd/even ?eld control bit from rtci logic 1 enable odd/even ?eld control bit from rtci (see fig.13) data byte description conditions remarks blnnl variable blanking level white-to-sync = 140 ire; note 1 recommended value: blnnl = 46 (2eh) blnnl = 0; note 1 output blanking level = 25 ire blnnl = 63 (3fh); note 1 output blanking level = 45 ire white-to-sync = 143 ire; note 2 recommended value: blnnl = 53 (35h) blnnl = 0; note 2 output blanking level = 26 ire blnnl = 63 (3fh); note 2 output blanking level = 46 ire decph real-time control logic 0 disable subcarrier phase reset bit from rtci logic 1 enable subcarrier phase reset bit from rtci (see fig.13) data byte description blnvb variable blanking level during vertical blanking interval is typically identical to value of blnnl ccrs select cross-colour reduction ?lter in luminance; see table 21
1999 may 31 17 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 21 logic levels and function of ccrs table 22 subaddress 61h table 23 subaddress 62ah ccrs1 ccrs0 description 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see fig.5 0 1 cross-colour reduction #1 active; for overall transfer characteristic see fig.5 1 0 cross-colour reduction #2 active; for overall transfer characteristic see fig.5 1 1 cross-colour reduction #3 active; for overall transfer characteristic see fig.5 data byte logic level description fise 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line pal 0 ntsc encoding (non-alternating v component) 1 pal encoding (alternating v component); default after reset scbw 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 3 and 4); default after reset ygs 0 luminance gain for white - black 100 ire; default after reset 1 luminance gain for white - black 92.5 ire including 7.5 ire set-up of black inpi 0 pal switch phase is nominal; default after reset 1 pal switch phase is inverted compared to nominal if rtc is enabled (see table 23) downa 0 dac for cvbs in normal operational mode; default after reset 1 dac for cvbs forced to lowest output voltage downb 0 dacs for r, g and b in normal operational mode 1 dacs for r, g and b forced to lowest output voltage; default after reset data byte logic level description rtce 0 no real-time control of generated subcarrier frequency; default after reset 1 real-time control of generated subcarrier frequency through saa7151b or saa7111; for timing see fig.13
1999 may 31 18 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 24 subaddress 62bh table 25 subaddresses 63h to 66h (four bytes to program subcarrier frequency) note 1. examples: a) ntsc-m: f fsc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal-b/g: f fsc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). table 26 subaddresses 67h to 6ah data byte description conditions remarks bsta amplitude of colour burst; input representation in accordance with ccir 601 white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding recommended value: bsta = 63 (3fh) bsta = 0 to 2.02 nominal white-to-black = 92.5 ire; burst = 40 ire; pal encoding recommended value: bsta = 45 (2dh) bsta = 0 to 2.82 nominal white-to-black = 100 ire; burst = 43 ire; ntsc encoding recommended value: bsta = 67 (43h) bsta = 0 to 1.90 nominal white-to-black = 100 ire; burst = 43 ire; pal encoding recommended value: bsta = 47 (2fh); default after reset bsta = 0 to 3.02 nominal data byte description conditions remarks fsc0 to fsc3 f fsc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency) ; note 1 fsc3 = most signi?cant byte; fsc0 = least signi?cant byte data byte description remarks l21o0 ?rst byte of captioning data, odd ?eld lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format. l21o1 second byte of captioning data, odd ?eld l21e0 ?rst byte of extended data, even ?eld l21e1 second byte of extended data, even ?eld fsc round f fsc f llc ------- - 2 32 ? ? ?? =
1999 may 31 19 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 27 subaddress 6bh table 28 logic levels and function of srcv1 table 29 subaddresses 6ch and 6dh data byte logic level description prcv2 0 polarity of rcv2 as output is active high, rising edge is taken when input, respectively; default after reset 1 polarity of rcv2 as output is active low, falling edge is taken when input, respectively orcv2 0 pin rcv2 is switched to input; default after reset 1 pin rcv2 is switched to output cblf 0 if orcv2 = high, pin rcv2 provides an href signal (horizontal reference pulse that is de?ned by rcv2s and rcv2e, also during vertical blanking interval); default after reset. if orcv2 = low and bit symp = low, the signal input to rcv2 is used for horizontal synchronization only (if trcv2 = 1); default after reset. 1 if orcv2 = high, pin rcv2 provides a composite-blanking-not signal, for example a reference pulse that is de?ned by rcv2s and rcv2e, excluding vertical blanking interval, which is de?ned by fal and lal. if orcv2 = low and bit symp = low, the signal input to rcv2 is used for horizontal synchronization (if trcv2 = 1) and as an internal blanking signal. prcv1 0 polarity of rcv1 as output is active high, rising edge is taken when input; default after reset 1 polarity of rcv1 as output is active low, falling edge is taken when input orcv1 0 pin rcv1 is switched to input; default after reset 1 pin rcv1 is switched to output trcv2 0 horizontal synchronization is taken from rcv1 port (at bit symp = low) or from decoded frame sync of ccir 656 input (at bit symp = high); default after reset 1 horizontal synchronization is taken from rcv2 port (at bit symp = low) srcv1 - de?nes signal type on pin rcv1; see table 28 data byte as output as input function srcv11 srcv10 0 0 vs vs vertical sync each ?eld; default after reset 0 1 fs fs frame sync (odd/even) 1 0 fseq fseq ?eld sequence, vertical sync every fourth ?eld (pal = 0) or eighth ?eld (pal = 1) 1 1 not applicable not applicable - data byte description htrig sets the horizontal trigger phase related to signal on rcv1 or rcv2 input values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed; increasing htrig decreases delays of all internally generated timing signals; reference mark: analog output horizontal sync (leading slope) coincides with active edge of rcv used for triggering at htrig = 39h
1999 may 31 20 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 30 subaddress 6dh table 31 subaddress 6eh table 32 logic levels and function of phres table 33 logic levels and function of ldel table 34 logic levels and function of flc data byte description vtrig sets the vertical trigger phase related to signal on rcv1 input increasing vtrig decreases delays of all internally generated timing signals, measured in half lines; variation range of vtri g=0to31 (1fh) data byte logic level description sblbn 0 vertical blanking is de?ned by programming of fal and lal; default after reset 1 vertical blanking is forced in accordance with ccir 624 (50 hz) or rs170a (60 hz) blckon 0 encoder in normal operation mode 1 output signal is forced to blanking level; default after reset phres - selects the phase reset mode of the colour subcarrier generator; see table 32 ldel - selects the delay on luminance path with reference to chrominance path; see table 33 flc - ?eld length control; see table 34 data byte description phres1 phres0 0 0 no reset or reset via rtci from saa7111 if bit rtce = 1; default after reset 0 1 reset every two lines 1 0 reset every eight ?elds 1 1 reset every four ?elds data byte description ldel1 ldel0 0 0 no luminance delay; default after reset 0 1 1 llc luminance delay 1 0 2 llc luminance delay 1 1 3 llc luminance delay data byte description flc1 flc0 0 0 interlaced 312.5 lines/?eld at 50 hz, 262.5 lines/?eld at 60 hz; default after reset 0 1 non-interlaced 312 lines/?eld at 50 hz, 262 lines/?eld at 60 hz 1 0 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz 1 1 non-interlaced 313 lines/?eld at 50 hz, 263 lines/?eld at 60 hz
1999 may 31 21 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 35 subaddress 6fh table 36 logic levels and function of ccen table 37 subaddresses 70h to 72h table 38 subaddress 73h table 39 subaddress 74h data byte logic level description ccen - enables individual line 21 encoding; see table 36 ttxen 0 disables teletext insertion; default after reset 1 enables teletext insertion sccln - selects the actual line, where closed caption or extended data are encoded; line = (sccln + 4) for m-systems; line = (sccln + 1) for other systems data byte description ccen1 ccen0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds data byte description rcv2s start of output signal on rcv2 pin values above 1715 (fise = 1) or [1727 (fise = 0)] are not allowed; ?rst active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at rcv2s = 11ah [0fdh] rcv2e end of output signal on rcv2 pin values above 1715 (fise = 1) or [1727 (fise = 0)] are not allowed; last active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at rcv2e = 694h (687h) data byte description remarks ttxhs start of signal on pin ttxrq; see fig.14 pal: ttxhs = 42h ntsc: ttxhs = 54h data byte description remarks ttxhl length of ttxrq window; only active at old ttx protocol: bit ttxo = 1 ttxhl = 0: ttxrq = 1398llc; ttxhl = 15: ttxrq = 1413llc ttxhd indicates the delay in clock cycles between rising edge of ttxrq output and valid data at pin ttx minimum value: ttxhd = 2
1999 may 31 22 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 40 subaddress 75h table 41 subaddresses 76h, 77h and 7ch table 42 subaddresses 78h, 79h and 7ch table 43 subaddress 7ch table 44 subaddresses 7ah to 7ch data byte description vs_s vertical sync shift between rcv1 and rcv2 (switched to output); in master mode it is possible to shift h-sync (rcv2; cblf = 0) against v-sync (rcv1; srcv1 = 00) standard value: vs_s = 3 csynca advanced composite sync against rgb output from 0llc to 31llc data byte description remarks ttxovs ?rst line of occurrence of signal on pin ttxrq in odd ?eld pal: ttxovs = 05h; ntsc: ttxovs = 06h line = (ttxovs + 4) for m-systems line = (ttxovs + 1) for other systems ttxove last line of occurrence of signal on pin ttxrq in odd ?eld pal: ttxove = 16h; ntsc: ttxove = 10h line = (ttxove + 3) for m-systems line = ttxove for other systems data byte description remarks ttxevs ?rst line of occurrence of signal on pin ttxrq in even ?eld pal: ttxevs = 04h; ntsc: ttxevs = 05h line = (ttxevs + 4) for m-systems line = (ttxevs + 1) for other systems ttxeve last line of occurrence of signal on pin ttxrq in even ?eld pal: ttxevs = 16h; ntsc: ttxevs = 10h line = (ttxeve + 3) for m-systems line = ttxeve for other systems data byte logic level description ttxo 0 new ttx protocol selected: at each rising edge of ttxrq a single ttx bit is requested see fig.14; default after reset 1 old ttx protocol selected: the encoder provides a window of ttxrq going high; the length of the window depends on the chosen ttx standard see fig.14 ttx60 0 enables nabts (fise = 1) or european ttx (fise = 0); default after reset 1 enables world standard teletext 60 hz (fise = 1) data byte description fal ?rst active line = fal + 4 for m-systems, = fal + 1 for other systems, measured in lines fal = 0 coincides with the ?rst ?eld synchronization pulse lal last active line = lal + 3 for m-systems, = lal for other system, measured in lines lal = 0 coincides with the ?rst ?eld synchronization pulse
1999 may 31 23 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h table 45 subaddresses 7eh and 7fh in subaddresses 5bh, 5ch, 5dh, 5eh and 62h all ire values are rounded up. slave transmitter table 46 slave transmitter (slave address 89h) table 47 subaddress 00h data byte description line individual lines in both ?elds (pal counting) can be disabled for insertion of teletext by the respective bits, disabled line = linexx (50 hz ?eld rate) this bit mask is effective only, if the lines are enabled by ttxovs/ttxove and ttxevs/ttxeve register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte 00h ver2 ver1 ver0 ccrdo ccrde 0 fseq o_e data byte logic level description ver - version identi?cation of the device: it will be changed with all versions of the ic that have different programming models; current version is 000 binary ccrdo 1 closed caption bytes of the odd ?eld have been encoded 0 the bit is reset after information has been written to the subaddresses 67h and 68h; it is set immediately after the data has been encoded ccrde 1 closed caption bytes of the even ?eld have been encoded 0 the bit is reset after information has been written to the subaddresses 69h and 6ah; it is set immediately after the data has been encoded fseq 1 during ?rst ?eld of a sequence (repetition rate: ntsc = 4 ?elds, pa l = 8 ?elds) 0 not ?rst ?eld of a sequence o_e 1 during even ?eld 0 during odd ?eld
1999 may 31 24 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) (1) scbw = 1. (2) scbw = 0. fig.3 chrominance transfer characteristic 1. (1) scbw = 1. (2) scbw = 0. handbook, halfpage 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 mbe735 1.2 f (mhz) g v (db) (1) (2) fig.4 chrominance transfer characteristic 2.
1999 may 31 25 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h handbook, full pagewidth 6 (1) (2) (4) (3) 8101214 6 0 024 mgd672 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) ccrs1 = 0; ccrs0 = 1. (2) ccrs1 = 1; ccrs0 = 0. (3) ccrs1 = 1; ccrs0 = 1. (4) ccrs1 = 0; ccrs0 = 0. fig.5 luminance transfer characteristic 1. handbook, halfpage 02 (1) 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) (1) ccrs1 = 0; ccrs0 = 0. fig.6 luminance transfer characteristic 2.
1999 may 31 26 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb708 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.7 luminance transfer characteristic in rgb. handbook, full pagewidth 6 8 10 12 14 6 0 024 mgb706 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) fig.8 colour difference transfer characteristic in rgb.
1999 may 31 27 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h htrig = 0 prcv2 = 0. trcv2 = 1. orcv2 = 0. fig.9 sync and video input timing. handbook, full pagewidth mhb500 55llc 51llc mp input rcv2 input cvbs output rcv2s = 0. prcv2 = 0. orcv2 = 1. fig.10 sync and video output timing. handbook, full pagewidth mhb501 49llc rcv2 output cvbs output
1999 may 31 28 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h characteristics v ddd = 3.0 to 3.6 v; t amb =0to70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit supplies v dda analog supply voltage 3.15 3.45 v v ddd digital supply voltage 3.0 3.6 v i dda analog supply current note 1 - 100 ma i ddd digital supply current v ddd = 3.3 v; note 1 - 46 ma inputs v il low-level input voltage (pins llc1, rcv1, rcv2, mp7 to mp0, rtci, sa, reset and ttx) - 0.5 +0.8 v v ih high-level input voltage (pins llc1, rcv1, rcv2, mp7 to mp0, rtci, sa, reset and ttx) 2.0 v ddd + 0.3 v i li input leakage current - 1 m a c i input capacitance clocks - 10 pf data - 8pf i/os at high-impedance - 8pf outputs; pins rcv1, rcv2 and ttxrq v ol low-level output voltage i ol =2ma - 0.4 v v oh high-level output voltage i oh = 2 ma 2.4 - v i 2 c-bus; sda and scl v il low-level input voltage - 0.5 0.3v dd(i2c) v v ih high-level input voltage 0.7v dd(i2c) v dd(i2c) + 0.3 v i i input current v i = low or high - 10 +10 m a v ol low-level output voltage (pin sda) i ol =3ma - 0.4 v i o output current during acknowledge 3 - ma clock timing (pins llc1 and xclk) t llc1 cycle time note 2 34 41 ns d duty factor t high /t llc1 llc1 input 40 60 % duty factor t high /t xclk xclk output typical 50% 40 60 % t r rise time note 2 - 5ns t f fall time note 2 - 6ns input timing; pins llc1, rcv1, rcv2, mp7 to mp0, rtci, sa and ttx t su;dat input data set-up time 6 - ns t hd;dat input data hold time 3 - ns crystal oscillator f n nominal frequency (usually 27 mhz) 3rd-harmonic - 30 mhz d f/f n permissible deviation of nominal frequency note 3 - 50 +50 10 - 6
1999 may 31 29 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h notes 1. at maximum supply voltage with highly active input signals. 2. the data is for both input and output direction. 3. if an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 4. for full digital range, without load, v dda = 3.3 v. the typical voltage swing is 1.45 v, the typical minimum output voltage (digital zero at dac) is 0.2 v. c rystal specification t amb ambient temperature 0 70 c c l load capacitance 8 - pf r s series resistance - 80 w c 1 motional capacitance (typical) 1.5 - 20% 1.5 + 20% ff c 0 parallel capacitance (typical) 3.5 - 20% 3.5 + 20% pf data and reference signal output timing c l output load capacitance 7.5 40 pf t h output hold time 4 - ns t d output delay time - 25 ns cvbs and rgb outputs v o(p-p) output signal voltage (peak-to-peak value) note 4 1.30 1.55 v d v o inequality of output signal voltages - 2% r s(int) internal serial resistance 1 3 w r l output load resistance 75 300 w b output signal bandwidth of dacs - 3db 10 - mhz le lf(i) low frequency integral linearity error of dacs - 3 lsb le lf(d) low frequency differential linearity error of dacs - 1 lsb t d(pipe)(mp) total pipeline delay from mp port 27 mhz - 51 llc symbol parameter conditions min. max. unit
1999 may 31 30 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h fig.11 clock data timing. handbook, full pagewidth mhb502 xclk 0.6 v 1.5 v 2.6 v 2.0 v 0.8 v 2.4 v 0.6 v input data output data not valid valid valid not valid valid valid llc1 0.8 v 1.5 v 2.4 v t high t high t llc1 t llc1 t d t hd; dat t h t su; dat t f t f t r t r the data demultiplexing phase is coupled to the internal horizontal phase. the phase of the rcv2 signal is programmed to tbf (tbf for 50 hz) in this example in output mode (rcv2s). handbook, full pagewidth mp(n) llc cb(0) y(0) cr(0) y(1) cb(2) rcv2 mgb699 fig.12 functional timing.
1999 may 31 31 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h explanation of rtci data bits 1. the hpll increment is not evaluated by SAA7126H; saa7127h. 2. the SAA7126H; saa7127h generates the subcarrier frequency from the fscpll increment if enabled (see item 7.). 3. the pal bit indicates the line with inverted (r - y) component of colour difference signal. 4. if the reset bit is enabled (rtce = 1; decph = 1; phres = 00), the phase of the subcarrier is reset in each line whenever the reset bit of rtci input is set to logic 1. 5. if the fise bit is enabled (rtce = 1; decfis = 1), the SAA7126H; saa7127h takes this bit instead of the fise bit in subaddress 61h. 6. if the odd/even bit is enabled (rtce = 1; decoe = 1), the SAA7126H; saa7127h ignores its internally generated odd/even flag and takes the odd/even bit from rtci input. 7. if the colour detection bit is enabled (rtce = 1; deccol = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the SAA7126H; saa7127h. in the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of fscpll increment. if the colour detection bit is disabled (rtce = 1; deccol = 0), the subcarrier frequency is evaluated out of fscpll increment, independent of the colour detection bit of rtci input. fig.13 rtci timing. (1) saa7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before fscpll increment. (2) saa7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit. (3) sequence bit: pal: 0 = (r - y) line normal, 1 = (r - y) line inverted; ntsc: 0 = no change. (4) reset bit: only from saa7111 and saa7112 decoder. (5) fise bit: 0 = 50 hz, 1 = 60 hz. (6) odd/even bit: odd_even from external. (7) colour detection: 0 = no colour detected, 1 = colour detected. (8) reserved bits: 229 with 50 hz systems, 226 with 60 hz systems. handbook, full pagewidth 128 13 14 19 67 64 69 72 74 68 01 0 0 22 rtci hpll increment (1) fscpll increment (2) h/l transition count start 4 bits reserved valid sample invalid sample not used in SAA7126H/27h 3 bits reserved 8/llc mhb503 low time slot: (3) (4) (6) (7) (8) (5)
1999 may 31 32 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h teletext timing time t fd is the time needed to interpolate input data ttx and insert it into the cvbs and vbs output signal, such that it appears at t ttx = 9.78 m s (pal) or t ttx = 10.5 m s (ntsc) after the leading edge of the horizontal synchronization pulse. time t d(pipe)(mp) is the pipeline delay time introduced by the source that is gated by ttxrq in order to deliver ttx data. this delay is programmable by register ttxhd. for every active high state at output pin ttxrq, a new teletext bit must be provided by the source (new protocol) or a window of ttxrq going high is provided and the number of teletext bits, depending on the chosen ttx standard, is requested at input pin ttx (old protocol). since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable (ttxhs and ttxhd), the ttx data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. time t i(ttxw) is the internally used insertion window for ttx data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 mbits/s (pal), 296 teletext bits at a text data rate of 5.7272 mbits/s (world standard ttx) or 288 teletext bits at a text data rate of 5.7272 mbits/s (nabts). the insertion window is not opened if the control bit ttxen is zero. using appropriate programming, all suitable lines of the odd field (ttxovs and ttxove) plus all suitable lines of the even field (ttxevs and ttxeve) can be used for teletext insertion. fig.14 teletext timing. handbook, full pagewidth t i(ttxw) t ttx t pd t fd cvbs/y ttx ttxrq (new) ttxrq (old) text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mhb504
1999 may 31 33 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... application information o ok, full pagewidth 2 w (1) 23 w 75 w agnd 23 red dac1 dac2 dac3 u r 0.70 v (p-p) (2) 23 w 75 w agnd green u g 0.70 v (p-p) (2) mhb505 23 w 75 w agnd agnd dgnd blue u b 0.70 v (p-p) (2) agnd 22, 32, 33 5, 18, 38 v dda1 to v dda3 + 3.3 v analog + 3.3 v digital v ssd1 to v ssd3 v ddd1 to v ddd3 v ssa1 to v ssa3 25, 28, 31 36 6, 17, 39 35 34 xtali xtal 10 pf 10 pf x1 use one capacitor for each v ddd use one capacitor for each v dda 2 w (1) 26 v dda4 2 w (1) 29 dac4 4.7 w 75 w agnd cvbs u cvbs 1.23 v (p-p) (2) 2 w (1) 30 0.1 m f agnd 0.1 m f dgnd dgnd 0.1 m f 0.1 m h 1 nf 3rd harmonic 27.0 mhz digital inputs and outputs SAA7126H saa7127h fig.15 application circuit. (1) typical value. (2) for 100 100 colour bar.
1999 may 31 34 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h analog output voltages the analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.375 v), the internal series resistor (typical value 2 w ), the external series resistor and the external load impedance. the digital output signals in front of the dacs under nominal conditions occupy different conversion ranges, as indicated in table 48 for a 100 100 colour bar signal. values for the external series resistors result in a 75 w load. table 48 digital output signals conversion range conversion range (peak-to-peak) cvbs, sync tip-to-peak carrier (digits) y (vbs) sync tip-to-white (digits) rgb (y) black-to-white at gdy = gdc = - 6 (digits) 1016 881 712
1999 may 31 35 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1999 may 31 36 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 may 31 37 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 may 31 38 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 may 31 39 philips semiconductors product speci?cation digital video encoder SAA7126H; saa7127h notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 65 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero 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& sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. 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philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 545006/01/pp40 date of release: 1999 may 31 document order number: 9397 750 05278

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